1. Field of the Invention
The present invention relates to stacked transistor structures, such as can be used in high density three-dimensional (3D) memory devices, and memory devices utilizing such structures.
2. Description of Related Art
FIG. 1A is a perspective illustration of a 3D NAND-flash memory device, which is described in co-pending U.S. patent application Ser. No. 13/078,311, which application is incorporated by reference as if fully set forth herein. The device illustrated in FIG. 1A includes stacks of alternating semiconductor lines and insulating lines. Insulating material is removed from the drawing to expose additional structure. For example, insulating lines are removed between the semiconductor lines, in the stacks, and are removed between the stacks of semiconductor lines.
A multilayer array is formed on an insulating layer, and includes a plurality of word lines 325-1, . . . , 325-n conformal with the plurality of stacks. The plurality of stacks includes semiconductor lines 312, 313, 314, and 315 in multiple planes. Semiconductor lines in the same plane are electrically coupled together by bit line structures (e.g. 302B).
The word line numbering shown in FIG. 1A, ascending from 325-1 to 325-N going from the back to the front of the overall structure, applies to even memory pages. For odd memory pages, the word line numbering descends from 325-N to 325-1 going from the back to the front of the overall structure.
Bit line structures 312A, 313A, 314A, and 315A terminate semiconductor lines, such as semiconductor lines 312, 313, 314, and 315. As illustrated, these bit line structures 312A, 313A, 314A, and 315A are electrically connected to different bit lines for connection to decoding circuitry to select planes within the array. These bit line structures 312A, 313A, 314A, and 315A can be patterned at the same time that the plurality of stacks is defined.
Bit line structures 302B, 303B, 304B, and 305B terminate semiconductor lines, such as semiconductor lines 302, 303, 304, and 305. As illustrated, these bit line structures 302B, 303B, 304B, and 305B are electrically connected to different bit lines for connection to decoding circuitry to select planes within the array. These bit line structures 302B, 303B, 304B, and 305B can be patterned at the same time that the plurality of stacks is defined.
Any given stack of semiconductor lines is coupled to either the bit line structures 312A, 313A, 314A, and 315A, or the bit line structures 302B, 303B, 304B, and 305B, but not both. A stack of semiconductor bit lines has one of the two opposite orientations of bit line end-to-source line end orientation, or source line end-to-bit line end orientation. For example, the stack of semiconductor lines 312, 313, 314, and 315 has bit line end-to-source line end orientation; and the stack of semiconductor lines 302, 303, 304, and 305 has source line end-to-bit line end orientation.
The stack of semiconductor lines 312, 313, 314, and 315 is terminated at one end by the bit line structures 312A, 313A, 314A, and 315A, passes through SSL gate structure 319, ground select line GSL 326, word lines 325-1 WL through 325-N WL, ground select line GSL 327, and is terminated at the other end by source line 328. The stack of semiconductor lines 312, 313, 314, and 315 does not reach the bit line structures 302B, 303B, 304B, and 305B.
The stack of semiconductor lines 302, 303, 304, and 305 is terminated at one end by the bit line structures 302B, 303B, 304B, and 305B, passes through SSL gate structure 309, ground select line GSL 327, word lines 325-N WL through 325-1 WL, ground select line GSL 326, and is terminated at the other end by a source line (obscured by other parts of the figure). The stack of semiconductor lines 302, 303, 304, and 305 does not reach the bit line structures 312A, 313A, 314A, and 315A.
A layer of memory material is disposed in interface regions at cross-points between surfaces of the semiconductor lines 312-315 and 302-305 and the plurality of word lines 325-1 through 325-n. Ground select lines GSL 326 and GSL 327 are conformal with the plurality of stacks, similar to the word lines.
Every stack of semiconductor lines is terminated at one end by bit line structures and at the other end by a source line. For example, the stack of semiconductor lines 312, 313, 314, and 315 is terminated at one end by bit line structures 312A, 313A, 314A, and 315A, and terminated on the other end by a source line 328. At the near end of the figure, every other stack of semiconductor lines is terminated by the bit line structures 302B, 303B, 304B, and 305B, and every other stack of semiconductor lines is terminated by a separate source line. At the far end of the figure, every other stack of semiconductor lines is terminated by the bit line structures 312A, 313A, 314A, and 315A, and every other stack of semiconductor lines is terminated by a separate source line.
Bit lines and string select lines are formed at the metals layers ML1, ML2, and ML3. Bit lines are coupled to a plane decoder (not shown). String select lines are coupled to a string select line decoder (not shown).
The ground select lines GSL 326 and 327 may be patterned during the same step that the word lines 325-1 through 325-n are defined. Ground select devices are formed at cross-points between surfaces of the plurality of stacks and ground select lines GSL 326 and 327. The SSL gate structures 319 and 309 may be patterned during the same step that the word lines 325-1 through 325-n are defined. String select devices are formed at cross-points between surfaces of the plurality of stacks and string select (SSL) gate structures 319 and 309. These devices are coupled to decoding circuitry for selecting the strings within particular stacks in the array.
In three-dimensional memory (3D) devices, such as the one illustrated by FIG. 1A, there is a relatively high resistance in semiconductor lines (e.g. 312-315 and 302-305) passing through the SSL gate structures (e.g. 319 and 309) and the ground select lines GSL (e.g. 326 and 327), degrading performance of the 3D memory devices.
It is desirable to provide a 3D memory device with lower resistance in semiconductor lines passing through the SSL gate structures and the ground select lines.